One of the packaging techniques for an integrated circuit (IC) device is referred to as a “flip-chip” package. A flip chip package, also referred to as controlled collapse chip connection (C4), is a method for interconnecting semiconductor devices, such as an IC chip and a micro electromechanical system (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is flowed to complete the interconnect.
SLC (surface laminar circuit) is a technology that applies thin film processes that effectively provide for the formation of fine lines and interconnections and microvias to a circuit board core to produce the wiring density called for by flip-chip mounting technologies. Because the circuitry is effectively facing downward, once a circuit design is fabricated onto a flip-chip style package, any changes to the circuit become problematic.
When it is desirable to effect a circuit change to a fabricated device, a technique referred to as “backside circuit editing” is performed to access the active portions of a circuit from the rear, or backside of the device package.
A known technique for backside circuit editing uses a focused ion beam (FIB) to access the circuitry after the part has been mechanically thinned. In an embodiment, a typical FIB uses a liquid metal ion source (LMIS) to produce a beam of Ga+ ions that is focused by a column of electron optics onto a sample surface. The optical column shapes the beam in magnitude (e.g., several picoamperes (pA) to many nanoamperes (nA)), voltage (e.g., tens of kilovolts (kV)), and size (e.g., several nanometers (nm) to several micrometers (μm)), and rasters the beam over an area (ranging from approximately one square micrometer (μm2) to approximately one square millimeter (mm2) to produce an image of the surface. In a typical application, the thickness of the bulk silicon substrate is approximately 770 μm. Typically, a protective lid and capacitors are removed from the device. Then, the bulk of the silicon is mechanically removed by applying a polishing medium to the silicon, and removing as much of the silicon as possible, without damaging the circuitry or the device. The final thickness of the bulk silicon after thinning is typically 100 μm but can be thicker or thinner if warranted. Unfortunately, such mechanical polishing often leads to the formation of cracks in the silicon that damage or destroy the circuit device.
While mechanical thinning of the device has enabled the development of effective backside circuit editing techniques, it has drawbacks, such as cracking, thermal consequences leading to poor heat dissipation, etc. These drawbacks compromise the performance of the device. Furthermore, the removal of the capacitors, which is necessary to thin the bulk silicon, also can lead to detrimental effects, such as performance changes, jitter, etc.
Several methods for milling small access holes through the approximately 770 μm thickness of the bulk silicon have been studied, but have failed to be useful due to an inability to determine the milling rate and depth of the access hole or cavity. Full-thickness backside circuit editing has not been brought to fruition because the milling rate and depth of the milled cavity used to access the circuitry can not be measured accurately.
Therefore, it would be desirable to have a way to access the desired circuitry for editing purposes, without the need for thinning the entire backside of the flip chip.